(a) Field of the Invention
The present invention is related to an integrated semiconductor device, and more particularly it pertains to an integrated semiconductor device including transistors having a triode-like unsaturated voltage-current characteristic and transistors having a bipolar-transistor-like saturated voltage-current characteristic.
(b) Description of the Prior Art
In the past, in the field of manufacture of integrated circuit devices, attempts have been made to carry out integration, in a common semiconductor substrate, of a vertical type junction field effect transistor (vertical JFET), a certain type of which is often referred to as a static induction transistor, and a lateral type or vertical type bipolar transistor, by forming these transistors relying on common forming techniques in many of their forming steps.
As is well known, a vertical JFET has the following excellent features and advantages which include: (a) high input impedance; (b) large transconductance G.sub.m ; (c) no minority carrier storage effect; (d) low series resistance of gate; (e) high breakdown voltage; (f) small inter-electrode capacitance; (g) low noise property; and (h) negative temperature property. Thus, a vertical JFET exhibits these features when applied to linear circuits and like devices. However, this vertical JFET is of the normally-on type, and accordingly this transistor has some difficulty in, for example, the biasing system and circuit connections. Thus, there is the need that this vertical JFET be combined with a bipolar transistor when an integrated circuit is formed by the use of this transistor. As a bipolar transistor which is to be combined with a vertical JFET as stated above, it is advantageous from the viewpoint of manufacture to use a lateral type bipolar transistor because of the simplicity in its formation. However, a lateral type bipolar transistor, by nature, does not provide for sufficient desirable characteristics in the light of its structure, and this bipolar transistor is used only for exhibiting very limited functions.
In contrast thereto, a vertical type bipolar transistor exhibits sufficient desirable characteristics structurally, and therefore it can be utilized to exhibit various functions. However, in case this vertical type bipolar transistor is applied to integration jointly with a vertical JFET, it is often the case that, for the purpose of simplifying the manufacturing steps, the collector and the drain, the base and the gate, and the emitter and the source of this bipolar transistor and said FET are formed by relying on a common epitaxial growth technique or common diffusion technique, respectively. Thus, some compromise with respect to their characteristics cannot be avoided. Especially, the width and the impurity concentration of the base region of the vertical type bipolar transistor constitute important parameters for the characteristics of this bipolar transistor. Nevertheless, these items are determined by taking into consideration the depth and the impurity concentration of the gate region of the vertical JFET. In this respect, the inherent characteristics of the vertical type bipolar transistor are subjected to limitations to some extent. In a similar way, the characteristics of said FET are also inevitably subjected to some limitations. In order to eliminate such limitations, it would be necessary to manufacture the vertical JFET and the vertical type bipolar transistor separately. This, however, will result in complicated manufacturing steps and accordingly will reduce the value and advantage of integration to half.
Recently, an improved arrangement for a vertical-structure bipolar transistor suitable for integration with a vertical JFET has been proposed by Terumoto NONAKA, one of the present inventors, in Japanese Patent Application No. 52-50258 (corresponding U.S. Ser. No. 899,588 filed on Apr. 24, 1978) entitled INTEGRATED LOGIC CIRCUIT ARRANGEMENT. This proposed bipolar transistor, surely, is easier to be formed integrally with the vertical JFET as compared with the known conventional vertical-structure bipolar transistor, but still cannot be formed by the same manufacturing steps as those for the vertical JFET. Also, when integrated with the vertical JFET, it is necessarily accompanied by some degradation in performance due to the limitation in the designing requirements of the vertical JFET.